Wireless communication networks are widely deployed to provide various communication services such as voice, packet data, broadcast, messaging, and so on. Examples of such wireless networks include Code Division Multiple Access (CDMA) networks, Time Division Multiple Access (TDMA) networks, Frequency Division Multiple Access (FDMA) networks, and Orthogonal FDMA (OFDMA) networks. These wireless networks may also utilize various radio technologies such as Wideband-CDMA (W-CDMA), cdma2000, and Global System for Mobile Communications (GSM).
Wireless devices used in such wireless networks include receiver sections for converting radio frequency (RF) signals received by an antenna to baseband signals for digital processing. FIG. 1 shows a portion of an exemplary receiver chain 100 in a wireless device. Wirelessly transmitted RF signals are received by antenna 102. The RF signals are amplified by an LNA (low noise amplifier) 104. The amplified signals are passed to an RF interstage bandpass filter 106, typically a surface acoustic-wave (SAW) filter, and the filtered signal is passed back to a mixer 108.
The LNA 104 and mixer 108 are typically provided on an integrated circuit (“IC” or “chip”) 110, whereas the bandpass filter 106 is typically provided off-chip. A matching network (MN) 112 may be provided for impedance matching in passing filtered signals from the bandpass filter 106 back to the chip 110. The signals from the matching network 112 are input as differential signals to an input stage 114 of the mixer 108, which downconverts the signal to baseband or some intermediate frequency.
The input stage 114 of the mixer may have a conventional common-gate only (CGO) configuration, as shown in FIG. 2. Differential input signals 202, 204, which are identical but 180° out of phase, from the matching network are provided at the sources of NMOS transistors 206, 208, respectively. The gates of NMOS transistors 206, 208 are coupled through resistors 210, 212, providing the “common-gate” aspect of the circuit. The gate of each NMOS transistor 206, 208 is also cross-coupled to the opposite input signal than that provided to its source. PMOS transistors 220, 222 are connected at their gates through resistors 224, 226 to a constant voltage Vg 228, and connected at their sources to supply voltage Vdd 230. The current generated through each NMOS transistor is due to the input signals at its gate and source. The current through each PMOS transistor is constant due to the constant voltages provided at its gate and source. The total current It is the sum of the current through the PMOS transistor and NMOS transistor on each column of the circuit.
For a CGO input stage, in order to achieve high gain, the transconductance gmn of the NMOS transistors must be relatively large, which requires a matching network with a very high Q matching factor. Consequently, a potential disadvantage for CGO input stage is high sensitivity to input Q matching factor.